802.11 MAC/PHY - IP Cores

The 802.11 MAC/PHY stack is built on multiple FPGA IP cores. These cores are packaged as Vivado IP Cores and can be instantiated in any supported Vivado design flow. Our Reference FPGA Design instantiates these cores in a Vivado IPI block diagram.

PHY Transmitter

The PHY Transmitter IP core implements a complete, real-time bytes-to-waveform pipeline in FPGA fabric.

• Radio agnostic interface
  • Simple digital baseband (IQ) and control interface
  • Supports IQ sample rates up to 1/4 core clock frequency
• 802.11 a/g/n waveforms
  • NONHT OFDM (all rates)
  • HTMF 20MHz OFDM (MCS 0-7)
• Detailed logging of every transmission
  • Sample-accurate timestamp
  • MAC state at time of transmission

PHY Receiver

The PHY Receiver IP core implements a complete, real-time waveform-to-bytes pipeline in FPGA fabric.

• 802.11a/b/g/n waveforms
  • DSSS (1-2 Mbps rates)
  • NONHT OFDM (all rates)
  • HTMF 20MHz OFDM (MCS 0-7)
• Rx sensitivity better than spec
• Detailed logging of every reception
  • Sample-accurate timestamp
  • Per-subcarrier channel estimates
  • CFO estimate

MAC Support Core

The MAC support core implements real-time blocks to support MAC implementations and manages real-time interaction with the Tx/Rx PHY cores.

• Fully-programable MAC logic
  • Hardare logic implements real-time states
  • Software defines full MAC protocol
• Medium idle/busy monitoring
• IFS timers
• Parallel Tx state machines for independent Data, Beacon and Control packet Tx

Platform Support Cores

The PHY and MAC cores are designed to be platform independent. We provide a number of additional cores to implement a fully-functional 802.11 node on reference platforms.

• AD9361 controller
  • Manages AD9361 control interfaces
  • AGC state control
  • Custom SPI master
  • Read/write registers from software
  • Real-time SPI writes for Tx/Rx switching
• User I/O controller
  • Manages LEDs, buttons, switches on dev boards
  • Debug header I/O for monitoring real-time MAC/PHY signals